Real-time Subtraction Procedure for Eliminating Power-line Interference from Ecg

Presented is the algorithm of the subtraction procedure for removing powerline interference from ECG signals. The existing MatLab prototype version is adapted for real time execution on DSP and programmable logic (FPGA) platforms. The algorithm is ported and experimented in case of odd sample number in one period of the interference. The corresponding formulas for even sample number are given too. Key moment is the use of the ongoing interference values, which are stored in a temporary buffer and then used for recalculating the filter’s coefficients. Test results of the prototype MatLab code and its two implementations (for DSP and FPGA) show that the presented real time algorithms successfully compensate the presence of powerline frequency interference the ECG signal. Given are the changes in the DSP port of the algorithm and the generated structure by the FPGA configuration code.